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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-06-24 10:48:01 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-06-24 10:48:01 +0000 |
| commit | 959a255dfbe085a47e00fd21c57e87ad4c92719e (patch) | |
| tree | 4fc1f73c3db9852fb2a73d403ceb3994af499c10 /hw/qdev-properties.c | |
| parent | 8dacfcb407aa83664bd875123d2ec86612758c22 (diff) | |
| parent | b2d06f9607e36333686b0e52a188881ce38495c7 (diff) | |
| download | focaccia-qemu-959a255dfbe085a47e00fd21c57e87ad4c92719e.tar.gz focaccia-qemu-959a255dfbe085a47e00fd21c57e87ad4c92719e.zip | |
Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: (33 commits)
target-arm: Remove ARM_CPUID_* macros
target-arm: Remove remaining old cp15 infrastructure
target-arm: Move block cache ops to new cp15 framework
target-arm: Remove c0_cachetype CPUARMState field
target-arm: Convert final ID registers
target-arm: Convert MPIDR
target-arm: Convert cp15 cache ID registers
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
target-arm: Convert cp15 crn=1 registers
target-arm: Convert cp15 crn=9 registers
target-arm: Convert cp15 crn=6 registers
target-arm: convert cp15 crn=7 registers
target-arm: Convert cp15 VA-PA translation registers
target-arm: Convert cp15 MMU TLB control
target-arm: Convert cp15 crn=15 registers
target-arm: Convert cp15 crn=10 registers
target-arm: Convert cp15 crn=13 registers
target-arm: Convert cp15 crn=2 registers
target-arm: Convert MMU fault status cp15 registers
target-arm: Convert cp15 c3 register
...
Diffstat (limited to 'hw/qdev-properties.c')
0 files changed, 0 insertions, 0 deletions