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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-08-13 12:05:42 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-08-20 00:38:48 +0200 |
| commit | 7ce9760d64e8a884f044f95a1f32f96c2e0fafa0 (patch) | |
| tree | 70d5d523103919afac5341adc8c63e1792e587da /hw/remote/message.c | |
| parent | 453ba4f675f751fe4dceaff57ac1ebf72f28f6d0 (diff) | |
| download | focaccia-qemu-7ce9760d64e8a884f044f95a1f32f96c2e0fafa0.tar.gz focaccia-qemu-7ce9760d64e8a884f044f95a1f32f96c2e0fafa0.zip | |
target/mips: Use correct MMU index in get_pte()
When refactoring page_table_walk_refill() in commit 4e999bf419
we missed the indirect call to cpu_mmu_index() in get_pte():
page_table_walk_refill()
-> get_pte()
-> cpu_ld[lq]_code()
-> cpu_mmu_index()
Since we don't mask anymore the modes in hflags, cpu_mmu_index()
can return UM or SM, while we only expect KM or ERL.
Fix by propagating ptw_mmu_idx to get_pte(), and use the
cpu_ld/st_code_mmu() API with the correct MemOpIdx.
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Reported-by: Waldemar Brodkorb <wbx@uclibc-ng.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2470
Fixes: 4e999bf419 ("target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240814090452.2591-3-philmd@linaro.org>
Diffstat (limited to 'hw/remote/message.c')
0 files changed, 0 insertions, 0 deletions