Merge tag 'pull-riscv-to-apply-20220422-1' of github.com:alistair23/qemu into staging

First RISC-V PR for QEMU 7.1

 * Add support for Ibex SPI to OpenTitan
 * Add support for privileged spec version 1.12.0
 * Use privileged spec version 1.12.0 for virt machine by default
 * Allow software access to MIP SEIP
 * Add initial support for the Sdtrig extension
 * Optimisations for vector extensions
 * Improvements to the misa ISA string
 * Add isa extenstion strings to the device tree
 * Don't allow `-bios` options with KVM machines
 * Fix NAPOT range computation overflow
 * Fix DT property mmu-type when CPU mmu option is disabled
 * Make RISC-V ACLINT mtime MMIO register writable
 * Add and enable native debug feature
 * Support 64bit fdt address.

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* tag 'pull-riscv-to-apply-20220422-1' of github.com:alistair23/qemu: (31 commits)
  hw/riscv: boot: Support 64bit fdt address.
  hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
  target/riscv: cpu: Enable native debug feature
  target/riscv: machine: Add debug state description
  target/riscv: csr: Hook debug CSR read/write
  target/riscv: cpu: Add a config option for native debug
  target/riscv: debug: Implement debug related TCGCPUOps
  hw/intc: riscv_aclint: Add reset function of ACLINT devices
  hw/intc: Make RISC-V ACLINT mtime MMIO register writable
  hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
  hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
  hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
  target/riscv/pmp: fix NAPOT range computation overflow
  hw/riscv: virt: Exit if the user provided -bios in combination with KVM
  target/riscv: Use cpu_loop_exit_restore directly from mmu faults
  target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
  target/riscv: Add isa extenstion strings to the device tree
  target/riscv: misa to ISA string conversion fix
  target/riscv: optimize helper for vmv<nr>r.v
  target/riscv: optimize condition assign for scale < 0
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

1 files changed, 7 insertions, 5 deletions

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0f179d3601..57a41df8e9 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -212,9 +212,9 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
     return *start + size;
 }
 
-uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
 {
-    uint32_t temp, fdt_addr;
+    uint64_t temp, fdt_addr;
     hwaddr dram_end = dram_base + mem_size;
     int ret, fdtsize = fdt_totalsize(fdt);
 
@@ -229,7 +229,7 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
      * Thus, put it at an 16MB aligned address that less than fdt size from the
      * end of dram or 3GB whichever is lesser.
      */
-    temp = MIN(dram_end, 3072 * MiB);
+    temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
     fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
 
     ret = fdt_pack(fdt);
@@ -285,13 +285,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
                                hwaddr start_addr,
                                hwaddr rom_base, hwaddr rom_size,
                                uint64_t kernel_entry,
-                               uint32_t fdt_load_addr, void *fdt)
+                               uint64_t fdt_load_addr, void *fdt)
 {
     int i;
     uint32_t start_addr_hi32 = 0x00000000;
+    uint32_t fdt_load_addr_hi32 = 0x00000000;
 
     if (!riscv_is_32bit(harts)) {
         start_addr_hi32 = start_addr >> 32;
+        fdt_load_addr_hi32 = fdt_load_addr >> 32;
     }
     /* reset vector */
     uint32_t reset_vec[10] = {
@@ -304,7 +306,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
         start_addr,                  /* start: .dword */
         start_addr_hi32,
         fdt_load_addr,               /* fdt_laddr: .dword */
-        0x00000000,
+        fdt_load_addr_hi32,
                                      /* fw_dyn: */
     };
     if (riscv_is_32bit(harts)) {