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| author | Paolo Bonzini <pbonzini@redhat.com> | 2025-02-06 13:13:23 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-05-20 08:18:53 +0200 |
| commit | 5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4 (patch) | |
| tree | 36f5337db1d440bde02e71f98abac5bfc452925f /hw/riscv/boot.c | |
| parent | 71fb3aa5ebba5ba822371f864a12dbcded08147d (diff) | |
| download | focaccia-qemu-5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4.tar.gz focaccia-qemu-5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4.zip | |
target/riscv: store RISCVCPUDef struct directly in the class
Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct and go through it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/riscv/boot.c')
| -rw-r--r-- | hw/riscv/boot.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 765b9e2b1a..828a867be3 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -37,7 +37,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); - return mcc->misa_mxl_max == MXL_RV32; + return mcc->def->misa_mxl_max == MXL_RV32; } /* |