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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-02-26 20:14:46 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-26 20:14:46 +0000 |
| commit | b11728dc3ae67ddedf34b7a4f318170e7092803c (patch) | |
| tree | 1ec73af509292d112a3bf543d1b827643e288e03 /hw/riscv/boot.c | |
| parent | 1270a3f57c9221080f3205a15964814ff8359ca9 (diff) | |
| parent | 8c89d50c10afdd98da82642ca5e9d7af4f1c18bd (diff) | |
| download | focaccia-qemu-b11728dc3ae67ddedf34b7a4f318170e7092803c.tar.gz focaccia-qemu-b11728dc3ae67ddedf34b7a4f318170e7092803c.zip | |
Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu into staging
Fourth RISC-V PR for QEMU 8.0, Attempt 2 * A triplet of cleanups to the kernel/initrd loader that avoids duplication between the various boards. * Weiwei Li, Daniel Henrique Barboza, and Liu Zhiwei have been added as reviewers. Thanks for the help! * A fix for PMP matching to avoid incorrectly appling the default permissions on PMP permission violations. * A cleanup to avoid an unnecessary avoid env_archcpu() in cpu_get_tb_cpu_state(). * Fixes for the vector slide instructions to avoid truncating 64-bit values (such as doubles) on 32-bit targets. # -----BEGIN PGP SIGNATURE----- # # iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmP5Br8THHBhbG1lckBk # YWJiZWx0LmNvbQAKCRAuExnzX7sYiT4RD/9hdSlQlR1g/2h4fbCJ3U0GvyNH0T7N # mt3AX8hFvmfR1O63qqVVebJSHM1dTm6WsA19vKE5tdtbjV5V8UZuBTSqYeRBSrLd # LK9IHhwv3k9OQ/EG8CgRo7HEMxAurpC26zTf3chnfwa1Wyl5XxCXNx5hPbhu18G9 # oxw0sBi51T0Tb+N6lOVVSfmiEZWLXRq+lDCZdV0j864brsSjo4x8VEGrLaFTOJLf # X4MW6vBI4Pcb7EGnHjj5WvRKsf8gdahdx8bSTjORIm8oGri9Iyw6Vrg2khuhjnuH # 99sD1O06cvrylp+sCOVei8H3S6/xCepQXUXnCBCd1/cetgV+olo+ZR78Z8ZjXPED # jhZ23lsDcge+4W141lsCiwLgzI0YO3Ac+84zQLIvcx16c8zow3G9FO9sTlBSsgnW # 0XJrsUF7AZB6quUSMytG7WK+OBizzCRwj7ItC+Mty68wLrei5lDVj8b0t8hAQEdr # dOb7jku+Dz8OspGZx1aDKKifGDO+Ppv4PjAM2G44OmkM824SvvFg8+FEr9NgbKbp # VgTZDCeVC6IEpzthKsK8WeompLo7Sc33KITqwMbGiyGs+gsnmgKP2bcTLF8YTlFk # dqFBWjo3tjH5oukgTLCSYY4xPaHR9q418vGAfRox15GtUVliQ9iL5oH47PVXg4U7 # YsNZ74nD1pUueg== # =Umli # -----END PGP SIGNATURE----- # gpg: Signature made Fri 24 Feb 2023 18:49:35 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu: target/riscv: Fix vslide1up.vf and vslide1down.vf target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() target/riscv: Smepmp: Skip applying default rules when address matches MAINTAINERS: Add some RISC-V reviewers target/riscv: Remove privileged spec version restriction for RVV hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/riscv/boot.c')
| -rw-r--r-- | hw/riscv/boot.c | 97 |
1 files changed, 61 insertions, 36 deletions
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c7e0e50bd8..52bf8e67de 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,12 +173,55 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename != NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, start, mem_size - start); + if (size == -1) { + size = load_image_targphys(filename, start, mem_size - start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong kernel_start_addr, + bool load_initrd, symbol_fn_t sym_cb) { const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt = machine->fdt; g_assert(kernel_filename != NULL); @@ -192,61 +235,43 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry = kernel_load_base; + goto out; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry = kernel_start_addr; + goto out; } error_report("could not load kernel '%s'", kernel_filename); exit(1); -} - -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename = machine->initrd_filename; - uint64_t mem_size = machine->ram_size; - void *fdt = machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename != NULL); +out: /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. + * For 32 bit CPUs 'kernel_entry' can be sign-extended by + * load_elf_ram_sym(). */ - start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + if (riscv_is_32bit(harts)) { + kernel_entry = extract64(kernel_entry, 0, 32); + } - size = load_ramdisk(filename, start, mem_size - start); - if (size == -1) { - size = load_image_targphys(filename, start, mem_size - start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); } - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); } + + return kernel_entry; } /* |