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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:17 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 84fcf3c15111de9f0c72efbb6bc0def264555c46 (patch) | |
| tree | 57567c453d5ea85f06f0c753aefa4fa0d9709eae /hw/riscv/microchip_pfsoc.c | |
| parent | 406fafd5d0f9a1c6a365ff1733c26a043b1c4877 (diff) | |
| download | focaccia-qemu-84fcf3c15111de9f0c72efbb6bc0def264555c46.tar.gz focaccia-qemu-84fcf3c15111de9f0c72efbb6bc0def264555c46.zip | |
hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/microchip_pfsoc.c')
| -rw-r--r-- | hw/riscv/microchip_pfsoc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 131eea1ef3..4627179cd3 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -48,9 +48,9 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_plic.h" #include "hw/riscv/microchip_pfsoc.h" #include "hw/intc/sifive_clint.h" +#include "hw/intc/sifive_plic.h" #include "sysemu/sysemu.h" /* |