diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2022-09-14 12:11:06 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-09-27 07:04:38 +1000 |
| commit | 277b210dd86636cc910bf6cd9a5477d01a10603f (patch) | |
| tree | 89d327e0332c45272ba5d97fdba033af1386f9ec /hw/riscv/opentitan.c | |
| parent | 4c0f0b6619126637e802f07c9fe8e9fffbc1c4bb (diff) | |
| download | focaccia-qemu-277b210dd86636cc910bf6cd9a5477d01a10603f.tar.gz focaccia-qemu-277b210dd86636cc910bf6cd9a5477d01a10603f.zip | |
target/riscv: Set the CPU resetvec directly
Instead of using our properties to set a config value which then might
be used to set the resetvec (depending on your timing), let's instead
just set the resetvec directly in the env struct.
This allows us to set the reset vec from the command line with:
-global driver=riscv.hart_array,property=resetvec,value=0x20000400
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220914101108.82571-2-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/opentitan.c')
0 files changed, 0 insertions, 0 deletions