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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-01-20 16:15:51 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:22 +1000 |
| commit | 3de1fb712a072992d72bc99c2b70978132ee44d0 (patch) | |
| tree | 67c66da7a03f6bba091239d35f9227282869e078 /hw/riscv/opentitan.c | |
| parent | 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b (diff) | |
| download | focaccia-qemu-3de1fb712a072992d72bc99c2b70978132ee44d0.tar.gz focaccia-qemu-3de1fb712a072992d72bc99c2b70978132ee44d0.zip | |
target/riscv: update disas.c for xnor/orn/andn and slli.uw
The decoding of the following instructions from Zb[abcs] currently
contains decoding/printing errors:
* xnor,orn,andn: the rs2 operand is not being printed
* slli.uw: decodes and prints the immediate shift-amount as a
register (e.g. 'shift-by-2' becomes 'sp') instead of
interpreting this as an immediate
This commit updates the instruction descriptions to use the
appropriate decoding/printing formats.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120151551.1022761-1-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/opentitan.c')
0 files changed, 0 insertions, 0 deletions