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| author | Vasilis Liaskovitis <vliaskovitis@suse.com> | 2025-06-18 23:35:42 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:49 +1000 |
| commit | 5625817e8b77715b18d0ce3bfcc59fb337e387d8 (patch) | |
| tree | 6fe19c4ba1b6887cddcfa69bd832a2ab1fef13c6 /hw/riscv/riscv-iommu.c | |
| parent | a1f44e0c59081afceb5e2b389b6de96602f73977 (diff) | |
| download | focaccia-qemu-5625817e8b77715b18d0ce3bfcc59fb337e387d8.tar.gz focaccia-qemu-5625817e8b77715b18d0ce3bfcc59fb337e387d8.zip | |
target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction
Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1 and rd arguments are x0. In this case, if the new property is true, only the vill bit will be set. See https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc#avl-encoding According to the spec, the above use cases are reserved, and "Implementations may set vill in either case." Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2422 Signed-off-by: Vasilis Liaskovitis <vliaskovitis@suse.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250618213542.22873-1-vliaskovitis@suse.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/riscv-iommu.c')
0 files changed, 0 insertions, 0 deletions