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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-04-25 08:23:08 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-05-19 13:39:29 +1000 |
| commit | f1304836ea9399253c67b09513fca30f9f4b223e (patch) | |
| tree | abd9db23065f5eeb37c1a760382e1d02920e78d7 /hw/riscv/riscv_hart.c | |
| parent | c26c4afd0ffde4f79216975ac34f419d0fcf6795 (diff) | |
| download | focaccia-qemu-f1304836ea9399253c67b09513fca30f9f4b223e.tar.gz focaccia-qemu-f1304836ea9399253c67b09513fca30f9f4b223e.zip | |
target/riscv: Pass ra to riscv_csrrw
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250425152311.804338-5-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/riscv_hart.c')
| -rw-r--r-- | hw/riscv/riscv_hart.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 333083a4f1..7f2676008c 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -72,7 +72,7 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) ret = riscv_csrr(env, csrno, (target_ulong *)val); } else if (strcmp(cmd, "set_csr") == 0) { ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, - MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); } g_assert(ret == RISCV_EXCP_NONE); |