summary refs log tree commit diff stats
path: root/hw/riscv/sifive_prci.c
diff options
context:
space:
mode:
authorBin Meng <bmeng.cn@gmail.com>2019-09-05 08:55:16 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-09-17 08:42:44 -0700
commit9a2551ed6f946e96cd54ea3f3499d785a1f27c3d (patch)
treee5fd710818cf96d5bef1c010c7fe8adc41d9445e /hw/riscv/sifive_prci.c
parentdf42fdd6cc0df027d6f52b9abbd9cddac8f7c453 (diff)
downloadfocaccia-qemu-9a2551ed6f946e96cd54ea3f3499d785a1f27c3d.tar.gz
focaccia-qemu-9a2551ed6f946e96cd54ea3f3499d785a1f27c3d.zip
riscv: sifive_test: Add reset functionality
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv/sifive_prci.c')
0 files changed, 0 insertions, 0 deletions