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| author | Bin Meng <bin.meng@windriver.com> | 2021-01-26 14:00:01 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-03-04 09:43:29 -0500 |
| commit | 0694dabe9763847f3010b54ab3ec7d367d2f0ff0 (patch) | |
| tree | a92f68117045ffa9455a2529bd5fe09e52791249 /hw/riscv/sifive_u.c | |
| parent | 62d1076678a4c3d2385cc492283061b710bb0a60 (diff) | |
| download | focaccia-qemu-0694dabe9763847f3010b54ab3ec7d367d2f0ff0.tar.gz focaccia-qemu-0694dabe9763847f3010b54ab3ec7d367d2f0ff0.zip | |
hw/ssi: Add SiFive SPI controller support
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
0 files changed, 0 insertions, 0 deletions