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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:20:12 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:48 -0700 |
| commit | 4b55bc2b5f7ff065da5d2b813ee5153c598d3764 (patch) | |
| tree | 8ed72442f9af80bb4b86e3add122d84f811f3bd3 /hw/riscv/sifive_u.c | |
| parent | 806c64b7b0e782b7f1414478486c67df718a0f00 (diff) | |
| download | focaccia-qemu-4b55bc2b5f7ff065da5d2b813ee5153c598d3764.tar.gz focaccia-qemu-4b55bc2b5f7ff065da5d2b813ee5153c598d3764.zip | |
riscv: sifive_u: Update UART base addresses and IRQs
This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
| -rw-r--r-- | hw/riscv/sifive_u.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9e698a11c4..b66eaef607 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -62,8 +62,8 @@ static const struct MemmapEntry { [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, }; |