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authorRichard Henderson <richard.henderson@linaro.org>2024-12-13 16:43:40 +0000
committerRichard Henderson <richard.henderson@linaro.org>2024-12-15 12:56:03 -0600
commit766bade2da0f9b1338cbe72aea114cd0922acfc5 (patch)
treeee29a71fb6f2784202c8b767c1f173249954b215 /hw/riscv/sifive_u.c
parent4ef4c30d2ef6d1dcfc58512e6ed273244dcd72cd (diff)
downloadfocaccia-qemu-766bade2da0f9b1338cbe72aea114cd0922acfc5.tar.gz
focaccia-qemu-766bade2da0f9b1338cbe72aea114cd0922acfc5.zip
hw/riscv: Constify all Property
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/riscv/sifive_u.c')
-rw-r--r--hw/riscv/sifive_u.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index c5e74126b1..124ffd4842 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -936,7 +936,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
 }
 
-static Property sifive_u_soc_props[] = {
+static const Property sifive_u_soc_props[] = {
     DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
     DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
     DEFINE_PROP_END_OF_LIST()