Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200825' into staging

This pull request first adds support for multi-socket NUMA RISC-V
machines. The Spike and Virt machines both support NUMA sockets.

This PR also updates the current experimental Hypervisor support to the
v0.6.1 spec.

# gpg: Signature made Tue 25 Aug 2020 19:47:41 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200825:
  target/riscv: Support the Virtual Instruction fault
  target/riscv: Return the exception from invalid CSR accesses
  target/riscv: Support the v0.6 Hypervisor extension CRSs
  target/riscv: Only support little endian guests
  target/riscv: Only support a single VSXL length
  target/riscv: Update the CSRs to the v0.6 Hyp extension
  target/riscv: Update the Hypervisor trap return/entry
  target/riscv: Fix the interrupt cause code
  target/riscv: Convert MSTATUS MTL to GVA
  target/riscv: Don't allow guest to write to htinst
  target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
  target/riscv: Allow generating hlv/hlvx/hsv instructions
  target/riscv: Allow setting a two-stage lookup in the virt status
  hw/riscv: virt: Allow creating multiple NUMA sockets
  hw/riscv: spike: Allow creating multiple NUMA sockets
  hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
  hw/riscv: Allow creating multiple instances of PLIC
  hw/riscv: Allow creating multiple instances of CLINT

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 18301e6fa5..a48046c6a0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -687,7 +687,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
 
     /* MMIO */
     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
-        plic_hart_config,
+        plic_hart_config, 0,
         SIFIVE_U_PLIC_NUM_SOURCES,
         SIFIVE_U_PLIC_NUM_PRIORITIES,
         SIFIVE_U_PLIC_PRIORITY_BASE,
@@ -703,7 +703,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
-        memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
+        memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {