diff options
| author | Alistair Francis <Alistair.Francis@wdc.com> | 2019-03-16 01:21:29 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:14:40 -0700 |
| commit | 8b1d0714bfdd1ac2704519200120e326cba31066 (patch) | |
| tree | 17ff482dcaff91116dd2a7e8f3f39d002c1a5152 /hw/riscv/sifive_u.c | |
| parent | d9360e96885dbd69ce4aa925d1701c7a10cf54ae (diff) | |
| download | focaccia-qemu-8b1d0714bfdd1ac2704519200120e326cba31066.tar.gz focaccia-qemu-8b1d0714bfdd1ac2704519200120e326cba31066.zip | |
riscv: sifive_u: Allow up to 4 CPUs to be created
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
| -rw-r--r-- | hw/riscv/sifive_u.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7bc25820fe..3199238ba0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -398,7 +398,10 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc = "RISC-V Board compatible with SiFive U SDK"; mc->init = riscv_sifive_u_init; - mc->max_cpus = 1; + /* The real hardware has 5 CPUs, but one of them is a small embedded power + * management CPU. + */ + mc->max_cpus = 4; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) |