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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-08-30 15:35:02 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-09-21 07:56:49 +1000 |
| commit | f436ecc3156dea7edce97e7c247e3667203f5c8b (patch) | |
| tree | 1ca775b95bfaa3f19cb76a7cff031ac9aa05c4e0 /hw/riscv/sifive_u.c | |
| parent | e5cc6aaeb51dd0d80e1f5a6d6a6808d6355958aa (diff) | |
| download | focaccia-qemu-f436ecc3156dea7edce97e7c247e3667203f5c8b.tar.gz focaccia-qemu-f436ecc3156dea7edce97e7c247e3667203f5c8b.zip | |
hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/sifive_u.c')
| -rw-r--r-- | hw/riscv/sifive_u.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6cc1a62b0f..6766edc1d0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -832,7 +832,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, - plic_hart_config, 0, + plic_hart_config, ms->smp.cpus, 0, SIFIVE_U_PLIC_NUM_SOURCES, SIFIVE_U_PLIC_NUM_PRIORITIES, SIFIVE_U_PLIC_PRIORITY_BASE, |