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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-25 14:07:25 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-12-13 15:27:08 +0100 |
| commit | 37bae93ce54cfa1eeb8c51c9fa883ad781e0853b (patch) | |
| tree | 88780001c721d37b759faf8f71d1774b95e4552c /hw/riscv/virt.c | |
| parent | d4ee9a113e36e90f76cfec892cb9aacd3cd11c17 (diff) | |
| download | focaccia-qemu-37bae93ce54cfa1eeb8c51c9fa883ad781e0853b.tar.gz focaccia-qemu-37bae93ce54cfa1eeb8c51c9fa883ad781e0853b.zip | |
hw/riscv/virt: Remove pointless GPEX_HOST() cast
No need to QOM-cast twice, since the intermediate value is not used. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20241125140535.4526-7-philmd@linaro.org>
Diffstat (limited to 'hw/riscv/virt.c')
| -rw-r--r-- | hw/riscv/virt.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 45a8c4f819..2feb851f15 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1140,23 +1140,21 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, dev = qdev_new(TYPE_GPEX_HOST); /* Set GPEX object properties for the virt machine */ - object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, ecam_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, ecam_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), - PCI_HOST_BELOW_4G_MMIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, mmio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, mmio_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), - PCI_HOST_ABOVE_4G_MMIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, high_mmio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, high_mmio_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, pio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, pio_size, NULL); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -1189,7 +1187,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); } - GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; + GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; return dev; } |