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| author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2024-01-30 19:08:44 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
| commit | a5cb044ca4fef8f24b1a585f3dd3719da88aa9e3 (patch) | |
| tree | 92c930062fab8bcf18fde538ae92ce74c297a9f6 /hw/riscv/virt.c | |
| parent | ac8c8b6d1e5618f8fd293d9e451d87fb0d3867b3 (diff) | |
| download | focaccia-qemu-a5cb044ca4fef8f24b1a585f3dd3719da88aa9e3.tar.gz focaccia-qemu-a5cb044ca4fef8f24b1a585f3dd3719da88aa9e3.zip | |
target/riscv: Use RISCVException as return type for all csr ops
The real return value type has been converted to RISCVException, but some function declarations still not. This patch makes all csr operation declarations use RISCVExcetion. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240130110844.437-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/virt.c')
0 files changed, 0 insertions, 0 deletions