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| author | Bin Meng <bin.meng@windriver.com> | 2020-10-28 13:30:05 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | e35d617919a76b92af799baa483c4ff0e7c090e3 (patch) | |
| tree | fc1c5ad91e365d55bad530875dec4f2c3dbacdbc /hw/riscv | |
| parent | a937b302831f12094437cdbdfc859bff9f093525 (diff) | |
| download | focaccia-qemu-e35d617919a76b92af799baa483c4ff0e7c090e3.tar.gz focaccia-qemu-e35d617919a76b92af799baa483c4ff0e7c090e3.zip | |
hw/riscv: microchip_pfsoc: Connect the IOSCB module
Previously IOSCB_CFG was created as an unimplemented device. With the new IOSCB model, its memory range is already covered by the IOSCB hence remove the previous unimplemented device creation in the SoC codes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/Kconfig | 1 | ||||
| -rw-r--r-- | hw/riscv/microchip_pfsoc.c | 13 |
2 files changed, 9 insertions, 5 deletions
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index c8e50bde99..8f043e38e0 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -5,6 +5,7 @@ config MICROCHIP_PFSOC bool select CADENCE_SDHCI select MCHP_PFSOC_DMC + select MCHP_PFSOC_IOSCB select MCHP_PFSOC_MMUART select MSI_NONBROKEN select SIFIVE_CLINT diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 3c504f7c03..438e0c464d 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -16,6 +16,7 @@ * 5) SiFive Platform DMA (Direct Memory Access Controller) * 6) GEM (Gigabit Ethernet MAC Controller) * 7) DMC (DDR Memory Controller) + * 8) IOSCB modules * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -118,7 +119,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, - [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, }; @@ -162,6 +163,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); + + object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); } static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) @@ -373,10 +376,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_ENVM_DATA].base, envm_data); - /* IOSCBCFG */ - create_unimplemented_device("microchip.pfsoc.ioscb.cfg", - memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, - memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); + /* IOSCB */ + sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, + memmap[MICROCHIP_PFSOC_IOSCB].base); } static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) |