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authorPeter Maydell <peter.maydell@linaro.org>2022-01-22 18:24:39 +0000
committerPeter Maydell <peter.maydell@linaro.org>2022-01-28 14:29:47 +0000
commit1611956bce06b0721ea949e24c089ef22967672a (patch)
treef46ff64a87548e4e64a71eaddc6e4d6c0092ad57 /hw/rtc/goldfish_rtc.c
parentd7d19c0aeb7d657c76c88913744ff53fc7e24c23 (diff)
downloadfocaccia-qemu-1611956bce06b0721ea949e24c089ef22967672a.tar.gz
focaccia-qemu-1611956bce06b0721ea949e24c089ef22967672a.zip
hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported
The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate
that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable
LPIs (as opposed to allowing LPIs to be enabled but not subsequently
disabled). Our implementation permits this, so advertise it
by setting CES to 1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-10-peter.maydell@linaro.org
Diffstat (limited to 'hw/rtc/goldfish_rtc.c')
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