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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2024-01-12 12:53:42 +0000 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2024-02-13 19:37:28 +0000 |
| commit | 3fd325a2de38655f8cc2139d428311f3bdd140ee (patch) | |
| tree | 3706474600e9ffe5483686ad0857647cbb27474f /hw/scsi/esp.c | |
| parent | 3ee9a475a51eb7687cfb58ad68ef820238c1c6e1 (diff) | |
| download | focaccia-qemu-3fd325a2de38655f8cc2139d428311f3bdd140ee.tar.gz focaccia-qemu-3fd325a2de38655f8cc2139d428311f3bdd140ee.zip | |
esp.c: move CMD_TI end of message phase detection to esp_do_dma() and do_dma_pdma_cb()
The existing check for TC == 0 is only valid during a TI command. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Helge Deller <deller@gmx.de> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240112125420.514425-51-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'hw/scsi/esp.c')
| -rw-r--r-- | hw/scsi/esp.c | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index f8c20d0584..9f787d12a8 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -555,14 +555,16 @@ static void do_dma_pdma_cb(ESPState *s) } } break; - } - /* ATN remains asserted until TC == 0 */ - if (esp_get_tc(s) == 0) { - esp_set_phase(s, STAT_CD); - s->rregs[ESP_RSEQ] = SEQ_CD; - s->rregs[ESP_RINTR] |= INTR_BS; - esp_raise_irq(s); + case CMD_TI | CMD_DMA: + /* ATN remains asserted until TC == 0 */ + if (esp_get_tc(s) == 0) { + esp_set_phase(s, STAT_CD); + s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RINTR] |= INTR_BS; + esp_raise_irq(s); + } + break; } break; @@ -675,14 +677,16 @@ static void esp_do_dma(ESPState *s) } } break; - } - /* ATN remains asserted until TC == 0 */ - if (esp_get_tc(s) == 0) { - esp_set_phase(s, STAT_CD); - s->rregs[ESP_RSEQ] = SEQ_CD; - s->rregs[ESP_RINTR] |= INTR_BS; - esp_raise_irq(s); + case CMD_TI | CMD_DMA: + /* ATN remains asserted until TC == 0 */ + if (esp_get_tc(s) == 0) { + esp_set_phase(s, STAT_CD); + s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RINTR] |= INTR_BS; + esp_raise_irq(s); + } + break; } break; |