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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2012-12-05 16:53:42 +1000 |
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| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2012-12-05 09:20:36 +0100 |
| commit | d4d230da08918183929c7d6cb54824b391536904 (patch) | |
| tree | 20778c617d57e72f4988c12d7a7bc448108d8361 /hw/sd.c | |
| parent | 16c6c80ac3a772b42a87b77dfdf0fdac7c607b0e (diff) | |
| download | focaccia-qemu-d4d230da08918183929c7d6cb54824b391536904.tar.gz focaccia-qemu-d4d230da08918183929c7d6cb54824b391536904.zip | |
xilinx_axienet: Implement R_IS behaviour
The interrupt status register R_IS is the standard clear-on-write behaviour. This was unimplemented and defaulting to updating the register to the written value. Implemented clear-on-write. Reported-by: Jason Wu <huanyu@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'hw/sd.c')
0 files changed, 0 insertions, 0 deletions