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| author | Anthony Liguori <aliguori@us.ibm.com> | 2013-06-03 13:24:25 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2013-06-03 13:24:25 -0500 |
| commit | 0ded1fe5f36765b97b15a7afebb6d04ddcc4771c (patch) | |
| tree | 5bed5d3f9ac15091b101cbc8223d548490eabbcb /hw/sd/sdhci.c | |
| parent | 8b779b368b3b45d5ed3160173499eeafee4d567c (diff) | |
| parent | 95669e69848eda87861e1ec3016562101542f543 (diff) | |
| download | focaccia-qemu-0ded1fe5f36765b97b15a7afebb6d04ddcc4771c.tar.gz focaccia-qemu-0ded1fe5f36765b97b15a7afebb6d04ddcc4771c.zip | |
Merge remote-tracking branch 'pmaydell/arm-devs.next' into staging
# By Peter Crosthwaite (20) and others # Via Peter Maydell * pmaydell/arm-devs.next: (24 commits) i.MX: Improve EPIT timer code. exynos4210.c: register rom_mem for memory migration hw/arm/exynos4210.c: convert chipid_and_omr to an mmio region i.MX: split GPT and EPIT timer implementation sd/sd.c: Fix "inquiry" ACMD41 sd/sdhci:ADMA: fix interrupt sd/sdhci.c: Fix bdata_read DPRINT message sd/sdhci: Fix Buffer Write Ready interrupt sd/sdhci.c: Only reset data_count on new commands xilinx_spips: lqspi: Fix byte/misaligned access xilinx_spips: lqspi: Push more data to tx-fifo xilinx_spips: Multiple debug verbosity levels xilinx_spips: Debug msgs for Snoop state xilinx_spips: Fix striping behaviour xilinx_spips: Fix CTRL register RW bits xilinx_spips: lqspi: Dont touch config register xilinx_spips: Implement automatic CS xilinx_spips: Add automatic start support xilinx_spips: Trash LQ page cache on mode change xilinx_spips: Fix QSPI FIFO size ... Message-id: 1370277021-26129-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/sd/sdhci.c')
| -rw-r--r-- | hw/sd/sdhci.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 91dc9b082d..e64899cafb 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -260,6 +260,7 @@ static void sdhci_send_command(SDHCIState *s) sdhci_update_irq(s); if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { + s->data_count = 0; sdhci_do_data_transfer(s); } } @@ -404,15 +405,14 @@ static void sdhci_write_block_to_card(SDHCIState *s) /* Next data can be written through BUFFER DATORT register */ s->prnsts |= SDHC_SPACE_AVAILABLE; - if (s->norintstsen & SDHC_NISEN_WBUFRDY) { - s->norintsts |= SDHC_NIS_WBUFRDY; - } /* Finish transfer if that was the last block of data */ if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || ((s->trnmod & SDHC_TRNS_MULTI) && (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { SDHCI_GET_CLASS(s)->end_data_transfer(s); + } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { + s->norintsts |= SDHC_NIS_WBUFRDY; } /* Generate Block Gap Event if requested and if not the last block */ @@ -730,6 +730,15 @@ static void sdhci_do_adma(SDHCIState *s) break; } + if (dscr.attr & SDHC_ADMA_ATTR_INT) { + DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr); + if (s->norintstsen & SDHC_NISEN_DMA) { + s->norintsts |= SDHC_NIS_DMA; + } + + sdhci_update_irq(s); + } + /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { @@ -752,15 +761,6 @@ static void sdhci_do_adma(SDHCIState *s) return; } - if (dscr.attr & SDHC_ADMA_ATTR_INT) { - DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr); - if (s->norintstsen & SDHC_NISEN_DMA) { - s->norintsts |= SDHC_NIS_DMA; - } - - sdhci_update_irq(s); - return; - } } /* we have unfinished business - reschedule to continue ADMA */ @@ -773,7 +773,6 @@ static void sdhci_do_adma(SDHCIState *s) static void sdhci_data_transfer(SDHCIState *s) { SDHCIClass *k = SDHCI_GET_CLASS(s); - s->data_count = 0; if (s->trnmod & SDHC_TRNS_DMA) { switch (SDHC_DMA_TYPE(s->hostctl)) { @@ -881,7 +880,8 @@ static uint32_t sdhci_read(SDHCIState *s, unsigned int offset, unsigned size) case SDHC_BDATA: if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { ret = SDHCI_GET_CLASS(s)->bdata_read(s, size); - DPRINT_L2("read %ub: addr[0x%04x] -> %u\n", size, offset, ret); + DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, offset, + ret, ret); return ret; } break; |