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| author | Prasad J Pandit <pjp@fedoraproject.org> | 2017-02-28 12:08:14 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-02-28 12:08:14 +0000 |
| commit | 8b20aefac4ee8874bb9c8826e4b30e1dc8cd7511 (patch) | |
| tree | a36c4b71c44afb871ffe1b87acea92e9d35f2eb9 /hw/sd/sdhci.c | |
| parent | 373442ea3a96249991cfad3fc0e83fca5f8558d5 (diff) | |
| download | focaccia-qemu-8b20aefac4ee8874bb9c8826e4b30e1dc8cd7511.tar.gz focaccia-qemu-8b20aefac4ee8874bb9c8826e4b30e1dc8cd7511.zip | |
sd: sdhci: mask transfer mode register value
In SDHCI protocol, the transfer mode register is defined to be of 6 bits. Mask its value with '0x0037' so that an invalid value could not be assigned. Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20170214185225.7994-2-ppandit@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/sd/sdhci.c')
| -rw-r--r-- | hw/sd/sdhci.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index da32b5f709..a65c77dbd3 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -119,6 +119,7 @@ (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ (SDHC_CAPAB_TOCLKFREQ)) +#define MASK_TRNMOD 0x0037 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) static uint8_t sdhci_slotint(SDHCIState *s) @@ -1050,7 +1051,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) if (!(s->capareg & SDHC_CAN_DO_DMA)) { value &= ~SDHC_TRNS_DMA; } - MASKED_WRITE(s->trnmod, mask, value); + MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD); MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); /* Writing to the upper byte of CMDREG triggers SD command generation */ |