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| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-03-22 21:43:57 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-03-22 21:43:57 +0100 |
| commit | d76bb73549fcac07524aea5135280ea533a94fd6 (patch) | |
| tree | 6c0939bd8f91d83061e7eb87bf8eee498bf542ff /hw/spapr_pci.h | |
| parent | 52ae646d4a3ebdcdcc973492c6a56f2c49b6578f (diff) | |
| parent | 9ca3f7f3160365de9030e1a6128a871625abe346 (diff) | |
| download | focaccia-qemu-d76bb73549fcac07524aea5135280ea533a94fd6.tar.gz focaccia-qemu-d76bb73549fcac07524aea5135280ea533a94fd6.zip | |
Merge branch 'ppc-for-upstream' of git://github.com/agraf/qemu
* 'ppc-for-upstream' of git://github.com/agraf/qemu: (58 commits)
target-ppc: Use NARROW_MODE macro for tlbie
target-ppc: Use NARROW_MODE macro for addresses
target-ppc: Use NARROW_MODE macro for comparisons
target-ppc: Use NARROW_MODE macro for branches
target-ppc: Fix add and subf carry generation in narrow mode
target-ppc: Use QOM method dispatch for MMU fault handling
target-ppc: Move ppc tlb_fill implementation into mmu_helper.c
target-ppc: Split user only code out of mmu_helper.c
mmu-hash64: Implement Virtual Page Class Key Protection
mmu-hash*: Merge translate and fault handling functions
mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug()
mmu-hash*: Correctly mask RPN from hash PTE
mmu-hash*: Clean up real address calculation
mmu-hash*: Clean up PTE flags update
mmu-hash64: Factor SLB N bit into permissions bits
mmu-hash*: Clean up permission checking
mmu-hash32: Remove nx from context structure
mmu-hash*: Don't update PTE flags when permission is denied
mmu-hash32: Don't look up page tables on BAT permission error
mmu-hash32: Cleanup BAT lookup
...
Diffstat (limited to 'hw/spapr_pci.h')
| -rw-r--r-- | hw/spapr_pci.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h index 8bb3c62c3d..8bd8a663c5 100644 --- a/hw/spapr_pci.h +++ b/hw/spapr_pci.h @@ -39,7 +39,6 @@ typedef struct sPAPRPHBState { int32_t index; uint64_t buid; - char *busname; char *dtbusname; MemoryRegion memspace, iospace; @@ -82,8 +81,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq); } -PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index, - const char *busname); +PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index); int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, |