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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-09-03 19:48:17 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-09-03 19:48:17 +0000
commit9b94dc325b1ab7de421a0419f324d8f8db55aeb4 (patch)
treee80b0d51bdce21247540cbdc5758446697b0e658 /hw/sparc32_dma.c
parentc6d46c200f72be7b9fba3e0f29fa8d6128aea4c9 (diff)
downloadfocaccia-qemu-9b94dc325b1ab7de421a0419f324d8f8db55aeb4.tar.gz
focaccia-qemu-9b94dc325b1ab7de421a0419f324d8f8db55aeb4.zip
better PCNET endianness support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2147 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/sparc32_dma.c')
-rw-r--r--hw/sparc32_dma.c42
1 files changed, 38 insertions, 4 deletions
diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index d8d7e6a83e..b17a12b9e7 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -69,22 +69,56 @@ void ledma_set_irq(void *opaque, int isr)
     pic_set_irq_new(s->intctl, s->leirq, isr);
 }
 
-void ledma_memory_read(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len)
+/* Note: on sparc, the lance 16 bit bus is swapped */
+void ledma_memory_read(void *opaque, target_phys_addr_t addr, 
+                       uint8_t *buf, int len, int do_bswap)
 {
     DMAState *s = opaque;
+    int i;
 
     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
-    sparc_iommu_memory_read(s->iommu, addr | s->dmaregs[7], buf, len);
+    addr |= s->dmaregs[7];
+    if (do_bswap) {
+        sparc_iommu_memory_read(s->iommu, addr, buf, len);
+    } else {
+        addr &= ~1;
+        len &= ~1;
+        sparc_iommu_memory_read(s->iommu, addr, buf, len);
+        for(i = 0; i < len; i += 2) {
+            bswap16s((uint16_t *)(buf + i));
+        }
+    }
 }
 
-void ledma_memory_write(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len)
+void ledma_memory_write(void *opaque, target_phys_addr_t addr, 
+                        uint8_t *buf, int len, int do_bswap)
 {
     DMAState *s = opaque;
+    int l, i;
+    uint16_t tmp_buf[32];
 
     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
-    sparc_iommu_memory_write(s->iommu, addr | s->dmaregs[7], buf, len);
+    addr |= s->dmaregs[7];
+    if (do_bswap) {
+        sparc_iommu_memory_write(s->iommu, addr, buf, len);
+    } else {
+        addr &= ~1;
+        len &= ~1;
+        while (len > 0) {
+            l = len;
+            if (l > sizeof(tmp_buf))
+                l = sizeof(tmp_buf);
+            for(i = 0; i < l; i += 2) {
+                tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
+            }
+            sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
+            len -= l;
+            buf += l;
+            addr += l;
+        }
+    }
 }
 
 void espdma_raise_irq(void *opaque)