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| author | Cédric Le Goater <clg@kaod.org> | 2019-09-25 16:32:30 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-10-15 18:09:04 +0100 |
| commit | d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6 (patch) | |
| tree | ffdc43a7753c3b77b0098c960f96395a39836976 /hw/sparc | |
| parent | 72d96f8e2288e4bc7b31011c0c3f00448e2cef19 (diff) | |
| download | focaccia-qemu-d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6.tar.gz focaccia-qemu-d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6.zip | |
aspeed/timer: Add support for control register 3
The AST2500 timer has a third control register that is used to implement a set-to-clear feature for the main control register. This models the behaviour expected by the AST2500 while maintaining the same behaviour for the AST2400. The vmstate version is not increased yet because the structure is modified again in the following patches. Based on previous work from Joel Stanley. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-6-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/sparc')
0 files changed, 0 insertions, 0 deletions