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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 21:41:20 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 21:41:20 +0100 |
| commit | 497d415d76b9f59fcae27f22df1ca2c3fa4df64e (patch) | |
| tree | e4c09699e7ad90a4ae2d2ece477c25a6569420e5 /hw/ssi/npcm7xx_fiu.c | |
| parent | e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7 (diff) | |
| parent | d1b6b7017572e8d82f26eb827a1dba0e8cf3cae6 (diff) | |
| download | focaccia-qemu-497d415d76b9f59fcae27f22df1ca2c3fa4df64e.tar.gz focaccia-qemu-497d415d76b9f59fcae27f22df1ca2c3fa4df64e.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201008-1' into staging
target-arm queue: * hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer * hw/arm/fsl-imx25: Fix a typo * hw/arm/sbsa-ref : Fix SMMUv3 Initialisation * hw/arm/sbsa-ref : allocate IRQs for SMMUv3 * hw/char/bcm2835_aux: Allow less than 32-bit accesses * hw/arm/virt: Implement kvm-steal-time * target/arm: Make '-cpu max' have a 48-bit PA # gpg: Signature made Thu 08 Oct 2020 21:40:31 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20201008-1: target/arm: Make '-cpu max' have a 48-bit PA hw/arm/virt: Implement kvm-steal-time tests/qtest: Restore aarch64 arm-cpu-features test hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init hw/arm/virt: Move post cpu realize check into its own function target/arm/kvm: Make uncalled stubs explicitly unreachable linux headers: sync to 5.9-rc7 hw/char/bcm2835_aux: Allow less than 32-bit accesses hw/arm/sbsa-ref : allocate IRQs for SMMUv3 hw/arm/sbsa-ref : Fix SMMUv3 Initialisation hw/arm/fsl-imx25: Fix a typo hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi/npcm7xx_fiu.c')
| -rw-r--r-- | hw/ssi/npcm7xx_fiu.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index 104e8f2b96..5040132b07 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -103,7 +103,8 @@ enum NPCM7xxFIURegister { * Returns the index of flash in the fiu->flash array. This corresponds to the * chip select ID of the flash. */ -static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash) +static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, + NPCM7xxFIUFlash *flash) { int index = flash - fiu->flash; @@ -113,20 +114,19 @@ static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash) } /* Assert the chip select specified in the UMA Control/Status Register. */ -static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id) +static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id) { trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id); if (cs_id < s->cs_count) { qemu_irq_lower(s->cs_lines[cs_id]); + s->active_cs = cs_id; } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: UMA to CS%d; this module has only %d chip selects", DEVICE(s)->canonical_path, cs_id, s->cs_count); - cs_id = -1; + s->active_cs = -1; } - - s->active_cs = cs_id; } /* Deassert the currently active chip select. */ @@ -206,7 +206,7 @@ static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v, NPCM7xxFIUFlash *f = opaque; NPCM7xxFIUState *fiu = f->fiu; uint32_t dwr_cfg; - int cs_id; + unsigned cs_id; int i; if (fiu->active_cs != -1) { |