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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-03-11 13:20:23 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-11 13:20:23 +0000 |
| commit | 0ca540dbaea142ec5c3e7a1d12db7139b8317f37 (patch) | |
| tree | 58856f1ab0e13749b2826639ea11fa28341278d1 /hw/ssi/xilinx_spips.c | |
| parent | ed9b103d3e3102f17791ca53d4a8b17a3de929de (diff) | |
| parent | 72c1d3af6e9c2745edfeaa71918a68bcee4b79db (diff) | |
| download | focaccia-qemu-0ca540dbaea142ec5c3e7a1d12db7139b8317f37.tar.gz focaccia-qemu-0ca540dbaea142ec5c3e7a1d12db7139b8317f37.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140310' into staging
target-arm queue: * implement WFE as yield (improves performance with emulated SMP) * fixes to avoid undefined behaviour shifting left into sign bit * libvixl format string fixes for 32 bit hosts * fix build error when intptr_t and tcg_target_long are different sizes (eg x32) * implement PMCCNTR register * fix incorrect setting of E bit in CPSR (broke booting under KVM on ARM) # gpg: Signature made Mon 10 Mar 2014 15:05:25 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140310: target-arm: Implement WFE as a yield operation hw/arm/musicpal: Avoid shifting left into sign bit hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit hw/arm/omap1.c: Avoid shifting left into sign bit pxa2xx: Don't shift into sign bit libvixl: Fix format strings for several int64_t values target-arm: Fix intptr_t vs tcg_target_long target-arm: Implements the ARM PMCCNTR register target-arm: Fix incorrect setting of E bit in CPSR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi/xilinx_spips.c')
| -rw-r--r-- | hw/ssi/xilinx_spips.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 6a287464bf..8977243725 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -43,7 +43,7 @@ /* config register */ #define R_CONFIG (0x00 / 4) -#define IFMODE (1 << 31) +#define IFMODE (1U << 31) #define ENDIAN (1 << 26) #define MODEFAIL_GEN_EN (1 << 17) #define MAN_START_COM (1 << 16) @@ -87,7 +87,7 @@ #define R_LQSPI_CFG (0xa0 / 4) #define R_LQSPI_CFG_RESET 0x03A002EB -#define LQSPI_CFG_LQ_MODE (1 << 31) +#define LQSPI_CFG_LQ_MODE (1U << 31) #define LQSPI_CFG_TWO_MEM (1 << 30) #define LQSPI_CFG_SEP_BUS (1 << 30) #define LQSPI_CFG_U_PAGE (1 << 28) |