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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2013-06-03 17:17:43 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-06-03 17:17:43 +0100 |
| commit | 2133a5f6b8f8941a6a3734c6c1990656553de76c (patch) | |
| tree | 886e8997b1b0625734040b6765b129736d59aeed /hw/ssi/xilinx_spips.c | |
| parent | 15408b428f5b4db56da555fbda4f1aaf40d77f4b (diff) | |
| download | focaccia-qemu-2133a5f6b8f8941a6a3734c6c1990656553de76c.tar.gz focaccia-qemu-2133a5f6b8f8941a6a3734c6c1990656553de76c.zip | |
xilinx_spips: Fix CTRL register RW bits
The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi/xilinx_spips.c')
| -rw-r--r-- | hw/ssi/xilinx_spips.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ea8a593214..3e9e76c165 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -56,6 +56,7 @@ #define CLK_PH (1 << 2) #define CLK_POL (1 << 1) #define MODE_SEL (1 << 0) +#define R_CONFIG_RSVD (0x7bf40000) /* interrupt mechanism */ #define R_INTR_STATUS (0x04 / 4) @@ -355,7 +356,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); break; case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; @@ -415,7 +416,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); if (value & MAN_START_COM) { man_start_com = 1; } |