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authorArtyom Tarasenko <atar4qemu@gmail.com>2012-04-03 17:49:04 +0200
committerBlue Swirl <blauwirbel@gmail.com>2012-04-04 19:20:40 +0000
commit23cf96e1971f04f21ec4bb048df4d9e2e9933018 (patch)
tree72f508ac49edce4bbb93c08dfa44aa6ee61764ca /hw/sun4u.c
parentf05f6b4adb4db3affb0cdd17383b0a7e905e66e1 (diff)
downloadfocaccia-qemu-23cf96e1971f04f21ec4bb048df4d9e2e9933018.tar.gz
focaccia-qemu-23cf96e1971f04f21ec4bb048df4d9e2e9933018.zip
Fix vector interrupt handling
Don't produce stray irq 5, don't overwrite ivec_data if still busy with
processing of the previous interrupt.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/sun4u.c')
-rw-r--r--hw/sun4u.c29
1 files changed, 16 insertions, 13 deletions
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 237e20c1bf..50bc0d2e57 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -309,19 +309,22 @@ static void cpu_set_ivec_irq(void *opaque, int irq, int level)
     CPUSPARCState *env = opaque;
 
     if (level) {
-        CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
-        env->interrupt_index = TT_IVEC;
-        env->pil_in |= 1 << 5;
-        env->ivec_status |= 0x20;
-        env->ivec_data[0] = (0x1f << 6) | irq;
-        env->ivec_data[1] = 0;
-        env->ivec_data[2] = 0;
-        cpu_interrupt(env, CPU_INTERRUPT_HARD);
-      } else {
-        CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
-        env->pil_in &= ~(1 << 5);
-        env->ivec_status &= ~0x20;
-        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+        if (!(env->ivec_status & 0x20)) {
+            CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
+            env->halted = 0;
+            env->interrupt_index = TT_IVEC;
+            env->ivec_status |= 0x20;
+            env->ivec_data[0] = (0x1f << 6) | irq;
+            env->ivec_data[1] = 0;
+            env->ivec_data[2] = 0;
+            cpu_interrupt(env, CPU_INTERRUPT_HARD);
+        }
+    } else {
+        if (env->ivec_status & 0x20) {
+            CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
+            env->ivec_status &= ~0x20;
+            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+        }
     }
 }