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| author | Michael Rolnik <mrolnik@gmail.com> | 2020-01-24 01:51:13 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-07-11 11:02:05 +0200 |
| commit | 5718cef05a0fe306646dd0481eb6ccf4fef3979e (patch) | |
| tree | 96b88602f3de54c4fd5f9b3b60e3ff74161c23fb /hw/timer/avr_timer16.c | |
| parent | 9732b024f79217fbc685895791c4897d14096ef3 (diff) | |
| download | focaccia-qemu-5718cef05a0fe306646dd0481eb6ccf4fef3979e.tar.gz focaccia-qemu-5718cef05a0fe306646dd0481eb6ccf4fef3979e.zip | |
target/avr: Add instruction translation - Bit and Bit-test Instructions
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-15-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/timer/avr_timer16.c')
0 files changed, 0 insertions, 0 deletions