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| author | Sergey Fedorov <serge.fdrv@gmail.com> | 2015-07-06 10:05:43 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-07-06 10:05:43 +0100 |
| commit | 2a6332d968297266dbabf9d33f959e3a5efdd0f9 (patch) | |
| tree | 42109e197fe96c7ee1192d1bd7dab498399f1dc2 /hw/timer/cadence_ttc.c | |
| parent | f50a1640fb82708a5d528dee1ace42a224b95b15 (diff) | |
| download | focaccia-qemu-2a6332d968297266dbabf9d33f959e3a5efdd0f9.tar.gz focaccia-qemu-2a6332d968297266dbabf9d33f959e3a5efdd0f9.zip | |
target-arm: fix write helper for TLBI ALLE1IS
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs in the same Inner Sharable domain, not just on the current CPU. So we must use tlbiall_is_write() here. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1435676538-31345-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer/cadence_ttc.c')
0 files changed, 0 insertions, 0 deletions