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| author | Axel Heider <axel.heider@hensoldt.net> | 2022-10-19 15:09:50 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-10-27 10:27:23 +0100 |
| commit | 7719419deb07a431455dfb0178480ef4be2d3e2c (patch) | |
| tree | 5f06f2d854ca0bdd860a5c5e184151b94c0b6b02 /hw/timer/imx_epit.c | |
| parent | 7764963b9239dc966122617cc8b61d4530d6ce2a (diff) | |
| download | focaccia-qemu-7719419deb07a431455dfb0178480ef4be2d3e2c.tar.gz focaccia-qemu-7719419deb07a431455dfb0178480ef4be2d3e2c.zip | |
target/imx: reload cmp timer outside of the reload ptimer transaction
When running seL4 tests (https://docs.sel4.systems/projects/sel4test) on the sabrelight platform, the timer tests fail. The arm/imx6 EPIT timer interrupt does not fire properly, instead of a e.g. second in can take up to a minute to finally see the interrupt. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1263 Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Message-id: 166663118138.13362.1229967229046092876-0@git.sr.ht Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer/imx_epit.c')
| -rw-r--r-- | hw/timer/imx_epit.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 2bf8c754b2..ec0fa440d7 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -275,10 +275,15 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, /* If IOVW bit is set then set the timer value */ ptimer_set_count(s->timer_reload, s->lr); } - + /* + * Commit the change to s->timer_reload, so it can propagate. Otherwise + * the timer interrupt may not fire properly. The commit must happen + * before calling imx_epit_reload_compare_timer(), which reads + * s->timer_reload internally again. + */ + ptimer_transaction_commit(s->timer_reload); imx_epit_reload_compare_timer(s); ptimer_transaction_commit(s->timer_cmp); - ptimer_transaction_commit(s->timer_reload); break; case 3: /* CMP */ |