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| author | Michael Davidsaver <mdavidsaver@gmail.com> | 2017-02-28 12:08:17 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-02-28 12:08:17 +0000 |
| commit | da6d674e509f0939b2960eef2ce1c3443e9736df (patch) | |
| tree | 2fd1b55f59a0c341fcc13837b7418350a3e69d82 /hw/timer/imx_gpt.c | |
| parent | 1004102a772744fbb31d8001ade0090be8b02a93 (diff) | |
| download | focaccia-qemu-da6d674e509f0939b2960eef2ce1c3443e9736df.tar.gz focaccia-qemu-da6d674e509f0939b2960eef2ce1c3443e9736df.zip | |
armv7m: Rewrite NVIC to not use any GIC code
Despite some superficial similarities of register layout, the M-profile NVIC is really very different from the A-profile GIC. Our current attempt to reuse the GIC code means that we have significant bugs in our NVIC. Implement the NVIC as an entirely separate device, to give us somewhere we can get the behaviour correct. This initial commit does not attempt to implement exception priority escalation, since the GIC-based code didn't either. It does fix a few bugs in passing: * ICSR.RETTOBASE polarity was wrong and didn't account for internal exceptions * ICSR.VECTPENDING was 16 too high if the pending exception was for an external interrupt * UsageFault, BusFault and MemFault were not disabled on reset as they are supposed to be Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: reworked, various bugs and stylistic cleanups] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'hw/timer/imx_gpt.c')
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