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| author | Alvin Chang <alvinga@andestech.com> | 2024-06-26 21:22:46 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-06-27 12:25:09 +1000 |
| commit | 72dec1666fe92b5a5932d7f5c26bdfc72e238bcb (patch) | |
| tree | 8ab1277df6fec1138ef868526e7cb23b2c12d83b /hw/timer/omap_synctimer.c | |
| parent | 5e20b88953b564145f586c052cf7a75dc77796b5 (diff) | |
| download | focaccia-qemu-72dec1666fe92b5a5932d7f5c26bdfc72e238bcb.tar.gz focaccia-qemu-72dec1666fe92b5a5932d7f5c26bdfc72e238bcb.zip | |
target/riscv: Apply modularized matching conditions for watchpoint
We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6 triggers for the watchpoints. This commit also changes the behavior of looping the triggers. In previous implementation, if we have a type 2 trigger and env->virt_enabled is true, we directly return false to stop the loop. Now we keep looping all the triggers until we find a matched trigger. Only load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240626132247.2761286-3-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/timer/omap_synctimer.c')
0 files changed, 0 insertions, 0 deletions