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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2024-05-08 14:06:49 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-06-19 12:42:03 +0200 |
| commit | 49eba52a52fec563af83a77d5ec5c59dba412127 (patch) | |
| tree | e2528608c1386ba7057d74ebea2c4c51ea670eaf /hw/timer/stm32f2xx_timer.c | |
| parent | 5f82fb2a3a71bb510b3e1b7229929d468c01740a (diff) | |
| download | focaccia-qemu-49eba52a52fec563af83a77d5ec5c59dba412127.tar.gz focaccia-qemu-49eba52a52fec563af83a77d5ec5c59dba412127.zip | |
hw/intc/loongson_ipi: Provide per core MMIO address spaces
The real IPI hardware have dedicated MMIO registers mapped into memory address space for every core. This is not used by LoongArch guest software but it is essential for CPU without IOCSR such as Loongson-3A1000. Implement it with existing infrastructure. Acked-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-ID: <20240605-loongson3-ipi-v3-2-ddd2c0e03fa3@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/timer/stm32f2xx_timer.c')
0 files changed, 0 insertions, 0 deletions