diff options
| author | Guenter Roeck <linux@roeck-us.net> | 2014-04-25 08:39:48 -0700 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2014-05-13 09:12:40 +1000 |
| commit | 7dfba6dfbf805cf99c4ae89f6194bc9205dfbefe (patch) | |
| tree | 5bbfcd2f02f1a0b819a0b91a812f2ac45989ebb8 /hw/timer/xilinx_timer.c | |
| parent | 12f7fb60863f5aae44fa7a6c1f52cbecd29d4e9c (diff) | |
| download | focaccia-qemu-7dfba6dfbf805cf99c4ae89f6194bc9205dfbefe.tar.gz focaccia-qemu-7dfba6dfbf805cf99c4ae89f6194bc9205dfbefe.zip | |
xilinx_timer: Fix writes into TCSR register
The TCSR register has only 11 valid bits. This is now used by the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1 and later to hang when run under qemu-microblaze. Mask valid bits before writing the register to solve the problem. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'hw/timer/xilinx_timer.c')
| -rw-r--r-- | hw/timer/xilinx_timer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 6113b975bf..3ff1da9caf 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr, if (value & TCSR_TINT) value &= ~TCSR_TINT; - xt->regs[addr] = value; + xt->regs[addr] = value & 0x7ff; if (value & TCSR_ENT) timer_enable(xt); break; |