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authorPeter Maydell <peter.maydell@linaro.org>2016-02-19 17:44:24 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-02-19 17:44:24 +0000
commit586d1a99ff1253ac97c07459743e952abfff2a54 (patch)
treed0f9a5204bde3fbbed8fa9fadbdee2bc204fa19f /hw/vfio/pci.c
parent3ba32c100a51fcfd0ff367a5c40d4e84e206dd3a (diff)
parentb58b17f744b5465d0fc76eba1be549a9f5704bab (diff)
downloadfocaccia-qemu-586d1a99ff1253ac97c07459743e952abfff2a54.tar.gz
focaccia-qemu-586d1a99ff1253ac97c07459743e952abfff2a54.zip
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20160219.1' into staging
VFIO updates 2016-02-19

 - AER pre-enable and misc fixes (Cao jin and Chen Fan)
 - PCI_CAP_LIST_NEXT & PCI_MSIX_FLAGS cleanup (Wei Yang)
 - AMD XGBE KVM platform passthrough (Eric Auger)

# gpg: Signature made Fri 19 Feb 2016 17:28:36 GMT using RSA key ID 3BB08B22
# gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>"
# gpg:                 aka "Alex Williamson <alex@shazbot.org>"
# gpg:                 aka "Alex Williamson <alwillia@redhat.com>"
# gpg:                 aka "Alex Williamson <alex.l.williamson@gmail.com>"

* remotes/awilliam/tags/vfio-update-20160219.1:
  vfio/pci: use PCI_MSIX_FLAGS on retrieving the MSIX entries
  hw/arm/sysbus-fdt: remove qemu_fdt_setprop returned value check
  hw/arm/sysbus-fdt: enable amd-xgbe dynamic instantiation
  hw/arm/sysbus-fdt: helpers for clock node generation
  device_tree: qemu_fdt_getprop_cell converted to use the error API
  device_tree: qemu_fdt_getprop converted to use the error API
  device_tree: introduce qemu_fdt_node_path
  device_tree: introduce load_device_tree_from_sysfs
  hw/vfio/platform: amd-xgbe device
  vfio/pci: replace 1 with PCI_CAP_LIST_NEXT to make code self-explain
  pcie_aer: expose pcie_aer_msg() interface
  aer: impove pcie_aer_init to support vfio device
  vfio: make the 4 bytes aligned for capability size
  pcie: modify the capability size assert

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/vfio/pci.c')
-rw-r--r--hw/vfio/pci.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 49f3d2d239..20b505f4ec 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -1207,7 +1207,7 @@ static int vfio_msix_early_setup(VFIOPCIDevice *vdev)
     }
 
     if (pread(fd, &ctrl, sizeof(ctrl),
-              vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) {
+              vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) {
         return -errno;
     }
 
@@ -1505,10 +1505,11 @@ static void vfio_unmap_bars(VFIOPCIDevice *vdev)
  */
 static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos)
 {
-    uint8_t tmp, next = 0xff;
+    uint8_t tmp;
+    uint16_t next = PCI_CONFIG_SPACE_SIZE;
 
     for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp;
-         tmp = pdev->config[tmp + 1]) {
+         tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) {
         if (tmp > pos && tmp < next) {
             next = tmp;
         }
@@ -1697,7 +1698,7 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos)
     int ret;
 
     cap_id = pdev->config[pos];
-    next = pdev->config[pos + 1];
+    next = pdev->config[pos + PCI_CAP_LIST_NEXT];
 
     /*
      * If it becomes important to configure capabilities to their actual
@@ -1711,7 +1712,7 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos)
      * pci_add_capability always inserts the new capability at the head
      * of the chain.  Therefore to end up with a chain that matches the
      * physical device, we insert from the end by making this recursive.
-     * This is also why we pre-caclulate size above as cached config space
+     * This is also why we pre-calculate size above as cached config space
      * will be changed as we unwind the stack.
      */
     if (next) {
@@ -1727,7 +1728,7 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos)
     }
 
     /* Use emulated next pointer to allow dropping caps */
-    pci_set_byte(vdev->emulated_config_bits + pos + 1, 0xff);
+    pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff);
 
     switch (cap_id) {
     case PCI_CAP_ID_MSI: