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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-09-04 17:22:34 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-04 17:22:34 +0100 |
| commit | a8b5ad8e1faef0d1bb3e550530328e8ec76fe87c (patch) | |
| tree | 8b975dc3f75a6e9ea184eb335a8e952ab4b7021e /hw/virtio/virtio-pci.c | |
| parent | 9de65783e188b6cc3816847e03602864921bf504 (diff) | |
| parent | eeb39263aa9b05b4ac3f8d8e957958071834a7b6 (diff) | |
| download | focaccia-qemu-a8b5ad8e1faef0d1bb3e550530328e8ec76fe87c.tar.gz focaccia-qemu-a8b5ad8e1faef0d1bb3e550530328e8ec76fe87c.zip | |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
virtio,vhost: fixes, features, cleanups. FLR support. Misc fixes, cleanups. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 04 Sep 2019 12:53:35 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: libvhost-user: introduce and use vu_has_protocol_feature() libvhost-user: fix SLAVE_SEND_FD handling virtio-pci: Add Function Level Reset support virtio-rng: change default backend to rng-builtin virtio-rng: Keep the default backend out of VirtIORNGConf rng-builtin: add an RNG backend that uses qemu_guest_getrandom() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/virtio/virtio-pci.c')
| -rw-r--r-- | hw/virtio/virtio-pci.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index ffb03728f9..c6b47a9c73 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -604,6 +604,10 @@ static void virtio_write_config(PCIDevice *pci_dev, uint32_t address, pci_default_write_config(pci_dev, address, val, len); + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) { + pcie_cap_flr_write_config(pci_dev, address, val, len); + } + if (range_covers_byte(address, len, PCI_COMMAND) && !(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { virtio_pci_stop_ioeventfd(proxy); @@ -1780,6 +1784,10 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) pcie_ats_init(pci_dev, 256); } + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) { + /* Set Function Level Reset capability bit */ + pcie_cap_flr_init(pci_dev); + } } else { /* * make future invocations of pci_is_express() return false @@ -1847,6 +1855,8 @@ static Property virtio_pci_properties[] = { VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_PM_BIT, true), + DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_INIT_FLR_BIT, true), DEFINE_PROP_END_OF_LIST(), }; |