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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-04-06 13:22:51 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-04-06 13:22:51 +0100 |
| commit | 259e909790c83995436938a2b7af464b5d63d4c3 (patch) | |
| tree | bd6668b5d28b6b2c50e0034ca4c6935296140c4f /hw/virtio | |
| parent | 109918d24a3bb9ed3d05beb34ea4ac6be443c138 (diff) | |
| parent | d83f46d189a26fa32434139954d264326f199a45 (diff) | |
| download | focaccia-qemu-259e909790c83995436938a2b7af464b5d63d4c3.tar.gz focaccia-qemu-259e909790c83995436938a2b7af464b5d63d4c3.zip | |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pc,virtio: last minute bugfixes Two last minute bugfixes. They are both designed to prevent compatibility headaches down the road. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 06 Apr 2021 12:13:07 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio-pci: compat page aligned ATS x86: rename oem-id and oem-table-id properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/virtio')
| -rw-r--r-- | hw/virtio/virtio-pci.c | 5 | ||||
| -rw-r--r-- | hw/virtio/virtio-pci.h | 5 |
2 files changed, 9 insertions, 1 deletions
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index c1b67cf6fc..b321604d9b 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1856,7 +1856,8 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) } if (proxy->flags & VIRTIO_PCI_FLAG_ATS) { - pcie_ats_init(pci_dev, last_pcie_cap_offset); + pcie_ats_init(pci_dev, last_pcie_cap_offset, + proxy->flags & VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED); last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF; } @@ -1933,6 +1934,8 @@ static Property virtio_pci_properties[] = { ignore_backend_features, false), DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_ATS_BIT, false), + DEFINE_PROP_BIT("x-ats-page-aligned", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT, true), DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true), DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags, diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h index d7d5d403a9..2446dcd9ae 100644 --- a/hw/virtio/virtio-pci.h +++ b/hw/virtio/virtio-pci.h @@ -42,6 +42,7 @@ enum { VIRTIO_PCI_FLAG_INIT_PM_BIT, VIRTIO_PCI_FLAG_INIT_FLR_BIT, VIRTIO_PCI_FLAG_AER_BIT, + VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT, }; /* Need to activate work-arounds for buggy guests at vmstate load. */ @@ -84,6 +85,10 @@ enum { /* Advanced Error Reporting capability */ #define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT) +/* Page Aligned Address space Translation Service */ +#define VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED \ + (1 << VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT) + typedef struct { MSIMessage msg; int virq; |