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authorRichard Henderson <rth@twiddle.net>2013-07-31 10:18:49 -0700
committerRichard Henderson <rth@twiddle.net>2013-09-25 07:46:32 -0700
commit5e1702b0742b7cc88e85dfe76c3ba5d1432312aa (patch)
tree752924c62457ed8c720d33836dde43ce5dd3314d /hw/xen/xen_backend.c
parentb0940da012c4c80145fdcf1730620f28ce80c2d8 (diff)
downloadfocaccia-qemu-5e1702b0742b7cc88e85dfe76c3ba5d1432312aa.tar.gz
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tcg-ppc64: Tidy register allocation order
Remove conditionalization from tcg_target_reg_alloc_order, relying on
reserved_regs to prevent register allocation that shouldn't happen.
So R11 is now present in reg_alloc_order for __APPLE__, but also now
reserved.

Sort reg_alloc_order into call-saved, call-clobbered, and parameters.
This reduces the effect of values getting spilled and reloaded before
function calls.

Whether or not it is reserved, R2 (TOC) is always call-clobbered.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'hw/xen/xen_backend.c')
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