diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2012-05-02 16:49:40 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-19 13:24:44 +0000 |
| commit | 306a571a2d75e32cd2eae5486c2714b7b7792a63 (patch) | |
| tree | a6e1b1e8a6587c808110024b35cc9631162ae4c7 /hw | |
| parent | 2a29ddee82029580fa85276767f73fedc30c8a0a (diff) | |
| download | focaccia-qemu-306a571a2d75e32cd2eae5486c2714b7b7792a63.tar.gz focaccia-qemu-306a571a2d75e32cd2eae5486c2714b7b7792a63.zip | |
hw/arm_gic: Add qdev property for GIC revision
GIC behaviour can be different between revision 1 and 2 of the architectural GIC specification; we also have to handle the legacy 11MPCore GIC, which is different again in some places. Introduce a qdev property so we can behave appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/a15mpcore.c | 1 | ||||
| -rw-r--r-- | hw/arm11mpcore.c | 2 | ||||
| -rw-r--r-- | hw/arm_gic.c | 10 | ||||
| -rw-r--r-- | hw/armv7m_nvic.c | 2 |
4 files changed, 15 insertions, 0 deletions
diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c index 5a7b365548..fc0a02ae86 100644 --- a/hw/a15mpcore.c +++ b/hw/a15mpcore.c @@ -44,6 +44,7 @@ static int a15mp_priv_init(SysBusDevice *dev) s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + qdev_prop_set_uint32(s->gic, "revision", 2); qdev_init_nofail(s->gic); busdev = sysbus_from_qdev(s->gic); diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index c528d7aa01..1bff3d3282 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -123,6 +123,8 @@ static int mpcore_priv_init(SysBusDevice *dev) s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + /* Request the legacy 11MPCore GIC behaviour: */ + qdev_prop_set_uint32(s->gic, "revision", 0); qdev_init_nofail(s->gic); /* Pass through outbound IRQ lines from the GIC */ diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 2ec10ce457..ad72ac65a9 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -119,8 +119,13 @@ typedef struct gic_state struct gic_state *backref[NCPU]; MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ uint32_t num_irq; + uint32_t revision; } gic_state; +/* The special cases for the revision property: */ +#define REV_11MPCORE 0 +#define REV_NVIC 0xffffffff + static inline int gic_get_current_cpu(gic_state *s) { if (s->num_cpu > 1) { @@ -880,6 +885,11 @@ static int arm_gic_init(SysBusDevice *dev) static Property arm_gic_properties[] = { DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1), DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32), + /* Revision can be 1 or 2 for GIC architecture specification + * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. + * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) + */ + DEFINE_PROP_UINT32("revision", gic_state, revision, 1), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 747e245c2a..4c130f113c 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -447,6 +447,8 @@ static int armv7m_nvic_init(SysBusDevice *dev) /* The NVIC always has only one CPU */ s->gic.num_cpu = 1; + /* Tell the common code we're an NVIC */ + s->gic.revision = 0xffffffff; gic_init(&s->gic, s->num_irq); /* The NVIC and system controller register area looks like this: * 0..0xff : system control registers, including systick |