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| author | Zhao Liu <zhao1.liu@intel.com> | 2024-11-27 00:30:45 +0800 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2024-12-28 14:42:52 +0300 |
| commit | f2ccc4149363ed52444efc975ed838d6757c775c (patch) | |
| tree | 1476a46d0cd38090b1dfef1f2253334a8d2e386c /hw | |
| parent | 6a4fa294ebe56aa09cf65430305c80415a4d73d9 (diff) | |
| download | focaccia-qemu-f2ccc4149363ed52444efc975ed838d6757c775c.tar.gz focaccia-qemu-f2ccc4149363ed52444efc975ed838d6757c775c.zip | |
hw/timer/hpet: Fix comment about capabilities register
HPETState.capability stores the emulated value for "general capabilities and id register" instead of "main counter register". Fix the comment to accurately reflect this. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/timer/hpet.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 2a45410c0d..1c8c6c69ef 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -736,7 +736,7 @@ static void hpet_realize(DeviceState *dev, Error **errp) timer->state = s; } - /* 64-bit main counter; LegacyReplacementRoute. */ + /* 64-bit General Capabilities and ID Register; LegacyReplacementRoute. */ s->capability = 0x8086a001ULL; s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; s->capability |= ((uint64_t)(HPET_CLK_PERIOD * FS_PER_NS) << 32); |