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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-05-03 14:23:41 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-05-28 08:08:48 +0100 |
| commit | 981f2beb161b9bcaeedc1f91ad22bff255856cb2 (patch) | |
| tree | f77dd987fb57005742cf2a74a7c330cbec02170c /include/accel/tcg/cpu-ops.h | |
| parent | a4027ed7d4becb4cb67c912c75ecd4846b148829 (diff) | |
| download | focaccia-qemu-981f2beb161b9bcaeedc1f91ad22bff255856cb2.tar.gz focaccia-qemu-981f2beb161b9bcaeedc1f91ad22bff255856cb2.zip | |
target: Use cpu_pointer_wrap_uint32 for 32-bit targets
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are all 32-bit targets. AVR is more complicated, but using a 32-bit wrap preserves current behaviour. Cc: Michael Rolnik <mrolnik@gmail.com> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Stafford Horne <shorne@gmail.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Max Filippov <jcmvbkbc@gmail.com> Tested-by Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/accel/tcg/cpu-ops.h')
| -rw-r--r-- | include/accel/tcg/cpu-ops.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 4f3b4fd3bc..dd8ea30016 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -326,6 +326,7 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); * Common pointer_wrap implementations. */ vaddr cpu_pointer_wrap_notreached(CPUState *, int, vaddr, vaddr); +vaddr cpu_pointer_wrap_uint32(CPUState *, int, vaddr, vaddr); #endif |