diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2013-03-05 15:35:17 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-05-13 13:21:51 +0200 |
| commit | 4a92a558f49cb0693e36bd6d4f9217f298045be2 (patch) | |
| tree | 931ba97c48f579e0c0abe0a45b23a0cecd816879 /include/exec/cpu-all.h | |
| parent | 7b4d915e11ae7afb2d42a8cae90db26bc0c142b8 (diff) | |
| download | focaccia-qemu-4a92a558f49cb0693e36bd6d4f9217f298045be2.tar.gz focaccia-qemu-4a92a558f49cb0693e36bd6d4f9217f298045be2.zip | |
cpu: make CPU_INTERRUPT_RESET available on all targets
On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'include/exec/cpu-all.h')
| -rw-r--r-- | include/exec/cpu-all.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index fb649a4029..9cab592dc5 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -381,6 +381,9 @@ CPUArchState *cpu_copy(CPUArchState *env); /* Debug event pending. */ #define CPU_INTERRUPT_DEBUG 0x0080 +/* Reset signal. */ +#define CPU_INTERRUPT_RESET 0x0400 + /* Several target-specific external hardware interrupts. Each target/cpu.h should define proper names based on these defines. */ #define CPU_INTERRUPT_TGT_EXT_0 0x0008 @@ -395,9 +398,8 @@ CPUArchState *cpu_copy(CPUArchState *env); instruction being executed. These, therefore, are not masked while single-stepping within the debugger. */ #define CPU_INTERRUPT_TGT_INT_0 0x0100 -#define CPU_INTERRUPT_TGT_INT_1 0x0400 -#define CPU_INTERRUPT_TGT_INT_2 0x0800 -#define CPU_INTERRUPT_TGT_INT_3 0x2000 +#define CPU_INTERRUPT_TGT_INT_1 0x0800 +#define CPU_INTERRUPT_TGT_INT_2 0x2000 /* First unused bit: 0x4000. */ |