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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-19 17:54:10 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-25 10:42:51 -0700 |
| commit | 7b0d792ce13c0e894ee32a94b321b329724c9a25 (patch) | |
| tree | 33af9d48755e45cc700a0a3a9963737ccb5084b4 /include/exec/cpu-all.h | |
| parent | 6e050d415662ca97b71410b8c4d91f789872b407 (diff) | |
| download | focaccia-qemu-7b0d792ce13c0e894ee32a94b321b329724c9a25.tar.gz focaccia-qemu-7b0d792ce13c0e894ee32a94b321b329724c9a25.zip | |
cputlb: Move ROM handling from I/O path to TLB path
It does not require going through the whole I/O path in order to discard a write. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/exec/cpu-all.h')
| -rw-r--r-- | include/exec/cpu-all.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d148bded35..ad9ab85eb3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -337,12 +337,15 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT | TLB_BSWAP) + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ + | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) /** * tlb_hit_page: return true if page aligned @addr is a hit against the |