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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-06-21 12:27:27 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-06-26 17:33:00 +0200 |
| commit | a0eaae08c7c6a59c185cf646b02f4167b2ac6ec0 (patch) | |
| tree | 06257b623f9014b19f62525cea3a5f4aa168412d /include/exec/cpu-all.h | |
| parent | 187ba6945345cedf2f343fcc33e5616186aebe9d (diff) | |
| download | focaccia-qemu-a0eaae08c7c6a59c185cf646b02f4167b2ac6ec0.tar.gz focaccia-qemu-a0eaae08c7c6a59c185cf646b02f4167b2ac6ec0.zip | |
accel/tcg: Renumber TLB_DISCARD_WRITE
Move to fill a hole in the set of bits. Reduce the total number of tlb bits by 1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/exec/cpu-all.h')
| -rw-r--r-- | include/exec/cpu-all.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b5618613cc..8018ce783e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -325,10 +325,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ #define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) -/* Set if TLB entry writes ignored. */ -#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) /* * Use this mask to check interception with an alignment mask |