Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging

Second RISC-V PR for QEMU 7.0

 - Fix illegal instruction when PMP is disabled
 - SiFive PDMA 64-bit support
 - SiFive PLIC cleanups
 - Mark Hypervisor extension as non experimental
 - Enable Hypervisor extension by default
 - Support 32 cores on the virt machine
 - Corrections for the Vector extension
 - Experimental support for 128-bit CPUs
 - stval and mtval support for illegal instructions

# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
  target/riscv: Implement the stval/mtval illegal instruction
  target/riscv: Fixup setting GVA
  target/riscv: Set the opcode in DisasContext
  target/riscv: actual functions to realize crs 128-bit insns
  target/riscv: modification of the trans_csrxx for 128-bit support
  target/riscv: helper functions to wrap calls to 128-bit csr insns
  target/riscv: adding high part of some csrs
  target/riscv: support for 128-bit M extension
  target/riscv: support for 128-bit arithmetic instructions
  target/riscv: support for 128-bit shift instructions
  target/riscv: support for 128-bit U-type instructions
  target/riscv: support for 128-bit bitwise instructions
  target/riscv: accessors to registers upper part and 128-bit load/store
  target/riscv: moving some insns close to similar insns
  target/riscv: setup everything for rv64 to support rv128 execution
  target/riscv: array for the 64 upper bits of 128-bit registers
  target/riscv: separation of bitwise logic and arithmetic helpers
  target/riscv: additional macros to check instruction support
  qemu/int128: addition of div/rem 128-bit operations
  exec/memop: Adding signed quad and octo defines
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

1 files changed, 11 insertions, 4 deletions

diff --git a/include/exec/memop.h b/include/exec/memop.h
index 04264ffd6b..2a885f3917 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -85,29 +85,36 @@ typedef enum MemOp {
     MO_UB    = MO_8,
     MO_UW    = MO_16,
     MO_UL    = MO_32,
+    MO_UQ    = MO_64,
+    MO_UO    = MO_128,
     MO_SB    = MO_SIGN | MO_8,
     MO_SW    = MO_SIGN | MO_16,
     MO_SL    = MO_SIGN | MO_32,
-    MO_Q     = MO_64,
+    MO_SQ    = MO_SIGN | MO_64,
+    MO_SO    = MO_SIGN | MO_128,
 
     MO_LEUW  = MO_LE | MO_UW,
     MO_LEUL  = MO_LE | MO_UL,
+    MO_LEUQ  = MO_LE | MO_UQ,
     MO_LESW  = MO_LE | MO_SW,
     MO_LESL  = MO_LE | MO_SL,
-    MO_LEQ   = MO_LE | MO_Q,
+    MO_LESQ  = MO_LE | MO_SQ,
 
     MO_BEUW  = MO_BE | MO_UW,
     MO_BEUL  = MO_BE | MO_UL,
+    MO_BEUQ  = MO_BE | MO_UQ,
     MO_BESW  = MO_BE | MO_SW,
     MO_BESL  = MO_BE | MO_SL,
-    MO_BEQ   = MO_BE | MO_Q,
+    MO_BESQ  = MO_BE | MO_SQ,
 
 #ifdef NEED_CPU_H
     MO_TEUW  = MO_TE | MO_UW,
     MO_TEUL  = MO_TE | MO_UL,
+    MO_TEUQ  = MO_TE | MO_UQ,
+    MO_TEUO  = MO_TE | MO_UO,
     MO_TESW  = MO_TE | MO_SW,
     MO_TESL  = MO_TE | MO_SL,
-    MO_TEQ   = MO_TE | MO_Q,
+    MO_TESQ  = MO_TE | MO_SQ,
 #endif
 
     MO_SSIZE = MO_SIZE | MO_SIGN,